<html><head>
<meta charset="iso-8859-1" content="Arm / ATMEL/ AT91 library / AT91SAM7S256" http-equiv="Content-Type">
<title>Hardware API Selector: AT91SAM7S256 Definitions</title>
</head>
<h1>Usart Peripheral</h1>
<null><a name="US1"></a><b>US1</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_USART">AT91S_USART</a>)</font></i><b>  0xFFFC4000 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_US1">AT91C_BASE_US1</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>7</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_US1">AT91C_ID_US1</a>)</font></i></font></td><td><font size="-1">USART 1</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>RXD1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA21_RXD1    ">AT91C_PA21_RXD1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 21</font></td><td><font size="-1">USART 1 Receive Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>DTR1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA27_DTR1    ">AT91C_PA27_DTR1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 27</font></td><td><font size="-1">USART 1 Data Terminal ready</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>DCD1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA26_DCD1    ">AT91C_PA26_DCD1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 26</font></td><td><font size="-1">USART 1 Data Carrier Detect</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>TXD1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA22_TXD1    ">AT91C_PA22_TXD1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 22</font></td><td><font size="-1">USART 1 Transmit Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RTS1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA24_RTS1    ">AT91C_PA24_RTS1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 24</font></td><td><font size="-1">USART 1 Ready To Send</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>SCK1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA23_SCK1    ">AT91C_PA23_SCK1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 23</font></td><td><font size="-1">USART 1 Serial Clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>DSR1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA28_DSR1    ">AT91C_PA28_DSR1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 28</font></td><td><font size="-1">USART 1 Data Set ready</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RI1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA29_RI1     ">AT91C_PA29_RI1     </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 29</font></td><td><font size="-1">USART 1 Ring Indicator</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>CTS1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA25_CTS1    ">AT91C_PA25_CTS1    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 25</font></td><td><font size="-1">USART 1 Clear To Send</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US1_CfgPMC">AT91F_US1_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for US1</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US1_CfgPIO">AT91F_US1_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive US1 signals</font></td></tr>
</null></table><br><br><a name="US0"></a><b>US0</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_USART">AT91S_USART</a>)</font></i><b>  0xFFFC0000 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_US0">AT91C_BASE_US0</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>6</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_US0">AT91C_ID_US0</a>)</font></i></font></td><td><font size="-1">USART 0</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>RXD0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA5_RXD0    ">AT91C_PA5_RXD0    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 5</font></td><td><font size="-1">USART 0 Receive Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>TXD0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA6_TXD0    ">AT91C_PA6_TXD0    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 6</font></td><td><font size="-1">USART 0 Transmit Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RTS0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA7_RTS0    ">AT91C_PA7_RTS0    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 7</font></td><td><font size="-1">USART 0 Ready To Send</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>SCK0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA2_SCK0    ">AT91C_PA2_SCK0    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: B Bit: 2</font></td><td><font size="-1">USART 0 Serial Clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>CTS0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA8_CTS0    ">AT91C_PA8_CTS0    </a>)</font></i></font></td><td><font size="-1"><a href="AT91SAM7S256_PIO.html#PIOA">PIOA</a>  Periph: A Bit: 8</font></td><td><font size="-1">USART 0 Clear To Send</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US0_CfgPMC">AT91F_US0_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for US0</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US0_CfgPIO">AT91F_US0_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive US0 signals</font></td></tr>
</null></table><br><br></null><a name="USART"></a><h2>USART Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_USART">AT91S_USART</a>)</font></i></h2>
<a name="USART"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_CR">US_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_MR">US_MR</a></font></td><td><font size="-1">Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_IER">US_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_IDR">US_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_IMR">US_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_CSR">US_CSR</a></font></td><td><font size="-1">Channel Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_RHR">US_RHR</a></font></td><td><font size="-1">Receiver Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_THR">US_THR</a></font></td><td><font size="-1">Transmitter Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_BRGR">US_BRGR</a></font></td><td><font size="-1">Baud Rate Generator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x24</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_RTOR">US_RTOR</a></font></td><td><font size="-1">Receiver Time-out Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x28</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_TTGR">US_TTGR</a></font></td><td><font size="-1">Transmitter Time-guard Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x40</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_FIDI">US_FIDI</a></font></td><td><font size="-1">FI_DI_Ratio Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_NER">US_NER</a></font></td><td><font size="-1">Nb Errors Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_USART.html#US_IF">US_IF</a></font></td><td><font size="-1">IRDA_FILTER Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1">US_RPR (<a href="AT91SAM7S256_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1">US_RCR (<a href="AT91SAM7S256_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1">US_TPR (<a href="AT91SAM7S256_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1">US_TCR (<a href="AT91SAM7S256_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1">US_RNPR (<a href="AT91SAM7S256_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1">US_RNCR (<a href="AT91SAM7S256_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x118</b></font></td><td><font size="-1">US_TNPR (<a href="AT91SAM7S256_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x11C</b></font></td><td><font size="-1">US_TNCR (<a href="AT91SAM7S256_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">US_PTCR (<a href="AT91SAM7S256_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">US_PTSR (<a href="AT91SAM7S256_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_EnableIt">AT91F_US_EnableIt</a></b></font></td><td><font size="-1">Enable USART IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_TxReady">AT91F_US_TxReady</a></b></font></td><td><font size="-1">Return 1 if a character can be written in US_THR</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_Baudrate">AT91F_US_Baudrate</a></b></font></td><td><font size="-1">Caluculate baud_value according to the main clock and the baud rate</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_SetBaudrate">AT91F_US_SetBaudrate</a></b></font></td><td><font size="-1">Set the baudrate according to the CPU clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_SendFrame">AT91F_US_SendFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_DisableRx">AT91F_US_DisableRx</a></b></font></td><td><font size="-1">Disable Receiver</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_Close">AT91F_US_Close</a></b></font></td><td><font size="-1">Close USART: disable IT disable receiver and transmitter, close PDC</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_DisableTx">AT91F_US_DisableTx</a></b></font></td><td><font size="-1">Disable Transmitter</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_SetIrdaFilter">AT91F_US_SetIrdaFilter</a></b></font></td><td><font size="-1">Set the value of IrDa filter tregister</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_RxReady">AT91F_US_RxReady</a></b></font></td><td><font size="-1">Return 1 if a character can be read in US_RHR</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_SetTimeguard">AT91F_US_SetTimeguard</a></b></font></td><td><font size="-1">Set USART timeguard</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_DisableIt">AT91F_US_DisableIt</a></b></font></td><td><font size="-1">Disable USART IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_EnableRx">AT91F_US_EnableRx</a></b></font></td><td><font size="-1">Enable receiving characters</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_EnableTx">AT91F_US_EnableTx</a></b></font></td><td><font size="-1">Enable sending characters</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_Configure">AT91F_US_Configure</a></b></font></td><td><font size="-1">Configure USART</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_ResetRx">AT91F_US_ResetRx</a></b></font></td><td><font size="-1">Reset Receiver and re-enable it</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_ReceiveFrame">AT91F_US_ReceiveFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_GetChar">AT91F_US_GetChar</a></b></font></td><td><font size="-1">Receive a character,does not check if a character is available</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_PutChar">AT91F_US_PutChar</a></b></font></td><td><font size="-1">Send a character,does not check if ready to send</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_ResetTx">AT91F_US_ResetTx</a></b></font></td><td><font size="-1">Reset Transmitter and re-enable it</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_US_Error">AT91F_US_Error</a></b></font></td><td><font size="-1">Return the error flag</font></td></tr>
</null></table></null><h2>USART Register Description</h2>
<null><a name="US_CR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_CR  <i>Control Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_CR">AT91C_US1_CR</a></i> 0xFFFC4000</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_CR">AT91C_US0_CR</a></i> 0xFFFC0000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RSTRX"></a><b>US_RSTRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTRX">AT91C_US_RSTRX</a></font></td><td><b>Reset Receiver</b><br>0 = No effect.<br>1 = The receiver logic is reset, disabling the receive function (RXDIS is set internally).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_RSTTX"></a><b>US_RSTTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTTX">AT91C_US_RSTTX</a></font></td><td><b>Reset Transmitter</b><br>0 = No effect.<br>1 = The transmitter logic is reset, disabling the transmit function (TXDIS and STPBRK are set internally).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_RXEN"></a><b>US_RXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXEN">AT91C_US_RXEN</a></font></td><td><b>Receiver Enable</b><br>0 = No effect.<br>1 = The receiver is enabled if RXDIS is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_RXDIS"></a><b>US_RXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXDIS">AT91C_US_RXDIS</a></font></td><td><b>Receiver Disable</b><br>0 = No effect.<br>1 = The receiver is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_TXEN"></a><b>US_TXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEN">AT91C_US_TXEN</a></font></td><td><b>Transmitter Enable</b><br>0 = No effect.<br>1 = The transmitter is enabled if TXDIS is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_TXDIS"></a><b>US_TXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXDIS">AT91C_US_TXDIS</a></font></td><td><b>Transmitter Disable</b><br>0 = No effect.<br>1 = The transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_RSTSTA"></a><b>US_RSTSTA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTSTA">AT91C_US_RSTSTA</a></font></td><td><b>Reset Status Bits</b><br>0 = No effect.<br>1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_STTBRK"></a><b>US_STTBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_STTBRK">AT91C_US_STTBRK</a></font></td><td><b>Start Break</b><br>0 = No effect.<br>1 = If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_STPBRK"></a><b>US_STPBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_STPBRK">AT91C_US_STPBRK</a></font></td><td><b>Stop Break</b><br>0 = No effect.<br>1 = If a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12-bit periods.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_STTTO"></a><b>US_STTTO</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_STTTO">AT91C_US_STTTO</a></font></td><td><b>Start Time-out</b><br>0 = No effect<br>1 = Start waiting for a character before clocking the time-out counter.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_SENDA"></a><b>US_SENDA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_SENDA">AT91C_US_SENDA</a></font></td><td><b>Send Address</b><br>0 = No effect.<br>1 = In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_RSTIT"></a><b>US_RSTIT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTIT">AT91C_US_RSTIT</a></font></td><td><b>Reset Iterations</b><br>Note: This bit only has an effect in ISO7816 Mode.<br>0 = No effect.<br>1 = Resets the status bit Iteration.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="US_RSTNACK"></a><b>US_RSTNACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTNACK">AT91C_US_RSTNACK</a></font></td><td><b>Reset Non Acknowledge</b><br>0 = No effect<br>1 = Resets the status bit Nack</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="US_RETTO"></a><b>US_RETTO</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RETTO">AT91C_US_RETTO</a></font></td><td><b>Rearm Time-out</b><br>0 = No effect<br>1 = Restart Time-out</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_DTREN"></a><b>US_DTREN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DTREN">AT91C_US_DTREN</a></font></td><td><b>Data Terminal ready Enable</b><br>0 = No effect.<br>1 = The DTR pin is forced to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DTRDIS"></a><b>US_DTRDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DTRDIS">AT91C_US_DTRDIS</a></font></td><td><b>Data Terminal ready Disable</b><br>0 = No effect.<br>1 = The DTR pin is forced to 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_RTSEN"></a><b>US_RTSEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RTSEN">AT91C_US_RTSEN</a></font></td><td><b>Request to Send enable</b><br>0 = No effect.<br>1 = The RTS pin is forced to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_RTSDIS"></a><b>US_RTSDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RTSDIS">AT91C_US_RTSDIS</a></font></td><td><b>Request to Send Disable</b><br>0 = No effect.<br>1 = The RTS pin is forced to 1.</td></tr>
</null></table>
<a name="US_MR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_MR  <i>Mode Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_MR">AT91C_US1_MR</a></i> 0xFFFC4004</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_MR">AT91C_US0_MR</a></i> 0xFFFC0004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">3..0</td><td align="CENTER"><a name="US_USMODE"></a><b>US_USMODE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE">AT91C_US_USMODE</a></font></td><td><b>Usart mode</b><br>The Baud Rate Clock used in mode IS07816 can be configured via the register FI_DI_RATIO.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_USMODE_NORMAL"></a><b>US_USMODE_NORMAL</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_NORMAL">AT91C_US_USMODE_NORMAL</a></font></td><td><br>Normal</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_USMODE_RS485"></a><b>US_USMODE_RS485</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_RS485">AT91C_US_USMODE_RS485</a></font></td><td><br>RS485</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_USMODE_HWHSH"></a><b>US_USMODE_HWHSH</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_HWHSH">AT91C_US_USMODE_HWHSH</a></font></td><td><br>Hardware Handshaking</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_USMODE_MODEM"></a><b>US_USMODE_MODEM</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_MODEM">AT91C_US_USMODE_MODEM</a></font></td><td><br>Modem</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="US_USMODE_ISO7816_0"></a><b>US_USMODE_ISO7816_0</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_ISO7816_0">AT91C_US_USMODE_ISO7816_0</a></font></td><td><br>ISO7816 protocol: T = 0</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="US_USMODE_ISO7816_1"></a><b>US_USMODE_ISO7816_1</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_ISO7816_1">AT91C_US_USMODE_ISO7816_1</a></font></td><td><br>ISO7816 protocol: T = 1</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="US_USMODE_IRDA"></a><b>US_USMODE_IRDA</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_IRDA">AT91C_US_USMODE_IRDA</a></font></td><td><br>IrDA</td></tr>
<tr><td align="CENTER">12</td><td align="CENTER"><a name="US_USMODE_SWHSH"></a><b>US_USMODE_SWHSH</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_USMODE_SWHSH">AT91C_US_USMODE_SWHSH</a></font></td><td><br>Software Handshaking</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5..4</td><td align="CENTER"><a name="US_CLKS"></a><b>US_CLKS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CLKS">AT91C_US_CLKS</a></font></td><td><b>Clock Selection (Baud Rate generator Input Clock</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CLKS_CLOCK"></a><b>US_CLKS_CLOCK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CLKS_CLOCK">AT91C_US_CLKS_CLOCK</a></font></td><td><br>Clock</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CLKS_FDIV1"></a><b>US_CLKS_FDIV1</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CLKS_FDIV1">AT91C_US_CLKS_FDIV1</a></font></td><td><br>fdiv1</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CLKS_SLOW"></a><b>US_CLKS_SLOW</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CLKS_SLOW">AT91C_US_CLKS_SLOW</a></font></td><td><br>slow_clock (ARM)</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CLKS_EXT"></a><b>US_CLKS_EXT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CLKS_EXT">AT91C_US_CLKS_EXT</a></font></td><td><br>External (SCK)</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7..6</td><td align="CENTER"><a name="US_CHRL"></a><b>US_CHRL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHRL">AT91C_US_CHRL</a></font></td><td><b>Clock Selection (Baud Rate generator Input Clock</b><br>Start, stop and parity bits are added to the character length.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHRL_5_BITS"></a><b>US_CHRL_5_BITS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHRL_5_BITS">AT91C_US_CHRL_5_BITS</a></font></td><td><br>Character Length: 5 bits</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHRL_6_BITS"></a><b>US_CHRL_6_BITS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHRL_6_BITS">AT91C_US_CHRL_6_BITS</a></font></td><td><br>Character Length: 6 bits</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHRL_7_BITS"></a><b>US_CHRL_7_BITS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHRL_7_BITS">AT91C_US_CHRL_7_BITS</a></font></td><td><br>Character Length: 7 bits</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHRL_8_BITS"></a><b>US_CHRL_8_BITS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHRL_8_BITS">AT91C_US_CHRL_8_BITS</a></font></td><td><br>Character Length: 8 bits</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_SYNC"></a><b>US_SYNC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_SYNC">AT91C_US_SYNC</a></font></td><td><b>Synchronous Mode Select</b><br>0 = USART operates in Asynchronous Mode.<br>1 = USART operates in Synchronous Mode</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..9</td><td align="CENTER"><a name="US_PAR"></a><b>US_PAR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR">AT91C_US_PAR</a></font></td><td><b>Parity type</b><br>When the PAR field is set to Even parity, the parity bit is set (&#147;1&#148;) if the data parity is Odd in order to ensure an even parity on the Data and Parity field.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_PAR_EVEN"></a><b>US_PAR_EVEN</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_EVEN">AT91C_US_PAR_EVEN</a></font></td><td><br>Even Parity</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_PAR_ODD"></a><b>US_PAR_ODD</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_ODD">AT91C_US_PAR_ODD</a></font></td><td><br>Odd Parity</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_PAR_SPACE"></a><b>US_PAR_SPACE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_SPACE">AT91C_US_PAR_SPACE</a></font></td><td><br>Parity forced to 0 (Space)</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_PAR_MARK"></a><b>US_PAR_MARK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_MARK">AT91C_US_PAR_MARK</a></font></td><td><br>Parity forced to 1 (Mark)</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="US_PAR_NONE"></a><b>US_PAR_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_NONE">AT91C_US_PAR_NONE</a></font></td><td><br>No Parity</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="US_PAR_MULTI_DROP"></a><b>US_PAR_MULTI_DROP</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_MULTI_DROP">AT91C_US_PAR_MULTI_DROP</a></font></td><td><br>Multi-drop mode</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="US_NBSTOP"></a><b>US_NBSTOP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_NBSTOP">AT91C_US_NBSTOP</a></font></td><td><b>Number of Stop bits</b><br>The interpretation of the number of stop bits depends on SYNC.<br>1.5 or 2 stop bits are reserved for the TX function. The RX function uses only the 1 stop bit (there is no check on the 2 stop bit time slot if NBSTOP = 10).<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_NBSTOP_1_BIT"></a><b>US_NBSTOP_1_BIT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_NBSTOP_1_BIT">AT91C_US_NBSTOP_1_BIT</a></font></td><td><br>1 stop bit</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_NBSTOP_15_BIT"></a><b>US_NBSTOP_15_BIT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_NBSTOP_15_BIT">AT91C_US_NBSTOP_15_BIT</a></font></td><td><br>Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_NBSTOP_2_BIT"></a><b>US_NBSTOP_2_BIT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_NBSTOP_2_BIT">AT91C_US_NBSTOP_2_BIT</a></font></td><td><br>2 stop bits</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="US_CHMODE"></a><b>US_CHMODE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE">AT91C_US_CHMODE</a></font></td><td><b>Channel Mode</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHMODE_NORMAL"></a><b>US_CHMODE_NORMAL</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_NORMAL">AT91C_US_CHMODE_NORMAL</a></font></td><td><br>Normal Mode: The USART channel operates as an RX/TX USART.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHMODE_AUTO"></a><b>US_CHMODE_AUTO</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_AUTO">AT91C_US_CHMODE_AUTO</a></font></td><td><br>Automatic Echo: Receiver Data Input is connected to the TXD pin.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHMODE_LOCAL"></a><b>US_CHMODE_LOCAL</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_LOCAL">AT91C_US_CHMODE_LOCAL</a></font></td><td><br>Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHMODE_REMOTE"></a><b>US_CHMODE_REMOTE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_REMOTE">AT91C_US_CHMODE_REMOTE</a></font></td><td><br>Remote Loopback: RXD pin is internally connected to TXD pin.</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_MSBF"></a><b>US_MSBF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_MSBF">AT91C_US_MSBF</a></font></td><td><b>Bit Order</b><br>0 = LSB First<br>1 = MSB First</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_MODE9"></a><b>US_MODE9</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_MODE9">AT91C_US_MODE9</a></font></td><td><b>9-bit Character length</b><br>0 = CHRL defines character length.<br>1 = 9-bit character length.<br>MODE9 has priority on character length.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_CKLO"></a><b>US_CKLO</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CKLO">AT91C_US_CKLO</a></font></td><td><b>Clock Output Select</b><br>0 = The USART does not drive the SCK pin.<br>1 = The USART drives the SCK pin if USCLKS[1] is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_OVER"></a><b>US_OVER</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVER">AT91C_US_OVER</a></font></td><td><b>Over Sampling Mode</b><br>0 = 16x Oversampling<br>1 = 8x Oversampling</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20</td><td align="CENTER"><a name="US_INACK"></a><b>US_INACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_INACK">AT91C_US_INACK</a></font></td><td><b>Inhibit Non Acknowledge</b><br>0 = The NACK is generated<br>1 = The NACK is not generated<br>Note: This bit will be used only in ISO7816 mode, protocol T = 0 receiver.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">21</td><td align="CENTER"><a name="US_DSNACK"></a><b>US_DSNACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSNACK">AT91C_US_DSNACK</a></font></td><td><b>Disable Successive NACK</b><br>0 = NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).<br>1 = Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="US_MAX_ITER"></a><b>US_MAX_ITER</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_MAX_ITER">AT91C_US_MAX_ITER</a></font></td><td><b>Number of Repetitions</b><br>0-7 This will operate in mode ISO7816, Protocol T=0 only</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">28</td><td align="CENTER"><a name="US_FILTER"></a><b>US_FILTER</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FILTER">AT91C_US_FILTER</a></font></td><td><b>Receive Line Filter</b><br>0 = The USART does not filter the receive line.<br>1 = The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).</td></tr>
</null></table>
<a name="US_IER"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_IER">AT91C_US1_IER</a></i> 0xFFFC4008</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_IER">AT91C_US0_IER</a></i> 0xFFFC0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
</null></table>
<a name="US_IDR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_IDR">AT91C_US1_IDR</a></i> 0xFFFC400C</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_IDR">AT91C_US0_IDR</a></i> 0xFFFC000C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
</null></table>
<a name="US_IMR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_IMR">AT91C_US1_IMR</a></i> 0xFFFC4010</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_IMR">AT91C_US0_IMR</a></i> 0xFFFC0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
</null></table>
<a name="US_CSR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_CSR  <i>Channel Status Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_CSR">AT91C_US1_CSR</a></i> 0xFFFC4014</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_CSR">AT91C_US0_CSR</a></i> 0xFFFC0014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="US_ITERATION"></a><b>US_ITERATION</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ITERATION">AT91C_US_ITERATION</a></font></td><td><b>Max number of Repetitions Reached</b><br>Note: This bit will operate only in IS07816 mode, Protocol T = 0.<br>0 = Max number of repetitions has not been reached.<br>1 = Max number of repetitions has been reached.<br>A repetition consists of transmitted characters or successive NACK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="US_NACK"></a><b>US_NACK</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_NACK">AT91C_US_NACK</a></font></td><td><b>Non Acknowledge</b><br>0 = A Non Acknowledge has not been detected.<br>1 = A Non Acknowledge has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="US_RIIC"></a><b>US_RIIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RIIC">AT91C_US_RIIC</a></font></td><td><b>Ring INdicator Input Change Flag</b><br>0 = No input change has been detected on the RI pin since the last read of US_CSR.<br>1 = An input change has been detected on the RI pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_DSRIC"></a><b>US_DSRIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSRIC">AT91C_US_DSRIC</a></font></td><td><b>Data Set Ready Input Change Flag</b><br>0 = No input change has been detected on the DSR pin since the last read of US_CSR.<br>1 = An input change has been detected on the DSR pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_DCDIC"></a><b>US_DCDIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DCDIC">AT91C_US_DCDIC</a></font></td><td><b>Data Carrier Flag</b><br>0 = No input change has been detected on the DCD pin since the last read of US_CSR.<br>1 = An input change has been detected on the DCD pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="US_CTSIC"></a><b>US_CTSIC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CTSIC">AT91C_US_CTSIC</a></font></td><td><b>Clear To Send Input Change Flag</b><br>0 = No input change has been detected on the CTS pin since the last read of US_CSR.<br>1 = An input change has been detected on the CTS pin.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20</td><td align="CENTER"><a name="US_RI"></a><b>US_RI</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RI">AT91C_US_RI</a></font></td><td><b>Image of RI Input</b><br>0 = RI is at 0.<br>1 = RI is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">21</td><td align="CENTER"><a name="US_DSR"></a><b>US_DSR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DSR">AT91C_US_DSR</a></font></td><td><b>Image of DSR Input</b><br>0 = DSR<br>1 = DSR is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22</td><td align="CENTER"><a name="US_DCD"></a><b>US_DCD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_DCD">AT91C_US_DCD</a></font></td><td><b>Image of DCD Input</b><br>0 = DCD is at 0.<br>1 = DCD is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23</td><td align="CENTER"><a name="US_CTS"></a><b>US_CTS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CTS">AT91C_US_CTS</a></font></td><td><b>Image of CTS Input</b><br>0 = CTS is at 0.<br>1 = CTS is at 1.</td></tr>
</null></table>
<a name="US_RHR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_RHR  <i>Receiver Holding Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RHR">AT91C_US1_RHR</a></i> 0xFFFC4018</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RHR">AT91C_US0_RHR</a></i> 0xFFFC0018</font></null></ul><br>Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.<a name="US_THR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_THR  <i>Transmitter Holding Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_THR">AT91C_US1_THR</a></i> 0xFFFC401C</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_THR">AT91C_US0_THR</a></i> 0xFFFC001C</font></null></ul><br>Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.<a name="US_BRGR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_BRGR  <i>Baud Rate Generator Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_BRGR">AT91C_US1_BRGR</a></i> 0xFFFC4020</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_BRGR">AT91C_US0_BRGR</a></i> 0xFFFC0020</font></null></ul><br>Clock Divisor:<br>0 Disables Clock<br>1 Clock Divisor Bypass<br>2 to 65535 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD)<br>Baud Rate (Synchronous Mode) = Selected Clock/CD<br>Notes: 1. In Synchronous Mode, when either external clock (clk_ext or fdiv1) is selected, the value programmed must be even to ensure a 50:50 mark:space ratio.<br>In Synchronous Mode, when the internal clock (clock) is selected, the CD can be even and the duty clock is 50:50.<br>2. Clock divisor bypass (CD = 1) must not be used when the internal clock (clock) is selected (USCLKS = 0).<br>3. In Asynchronous Mode, the divisor of Selected Clock depends upon the value of the bit, OVER in US_MR.<a name="US_RTOR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_RTOR  <i>Receiver Time-out Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_RTOR">AT91C_US1_RTOR</a></i> 0xFFFC4024</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_RTOR">AT91C_US0_RTOR</a></i> 0xFFFC0024</font></null></ul><br>Time-out Value:<br>0 Disables the RX Time-out function.<br>1-65535 The Time-out counter is loaded with TO (16 bits) when the Start Time-out command is given or when each new data character is received (after reception has started).<a name="US_TTGR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_TTGR  <i>Transmitter Time-guard Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_TTGR">AT91C_US1_TTGR</a></i> 0xFFFC4028</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_TTGR">AT91C_US0_TTGR</a></i> 0xFFFC0028</font></null></ul><br>Time-guard duration = TG x Bit Period:<br>0 Disables the TX Time-out function.<br>1-255 TXD is inactive high after the transmission of each character for the time-guard duration.<a name="US_FIDI"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_FIDI  <i>FI_DI_Ratio Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_FIDI">AT91C_US1_FIDI</a></i> 0xFFFC4040</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_FIDI">AT91C_US0_FIDI</a></i> 0xFFFC0040</font></null></ul><br>Parameter used in mode ISO7816 to generate a specific bit rate<br>0 Baud Rate = 0<br>1-2047 Baud Rate = selected clock/FI_DI_RATIO/16<a name="US_NER"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_NER  <i>Nb Errors Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_NER">AT91C_US1_NER</a></i> 0xFFFC4044</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_NER">AT91C_US0_NER</a></i> 0xFFFC0044</font></null></ul><br>This 8-bit register presents the total amount of errors that occurred during an ISO7816 transfer. It is a read-only register and it is reset by reading the register.<a name="US_IF"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> US_IF  <i>IRDA_FILTER Register</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="AT91SAM7S256_h.html#AT91C_US1_IF">AT91C_US1_IF</a></i> 0xFFFC404C</font><font size="-2"><li><b>US0</b> <i><a href="AT91SAM7S256_h.html#AT91C_US0_IF">AT91C_US0_IF</a></i> 0xFFFC004C</font></null></ul><br>0-155 Parameter to reject pulses on IrDa reception<a name="US_PDC"></a><h4><a href="#USART">USART</a>: <i><a href="AT91SAM7S256_h.html#AT91S_PDC">AT91S_PDC</a></i> US_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>US1</b> <i><a href="#AT91C_US1_US">AT91C_US1_US</a></i> 0xFFFC4100</font><font size="-2"><li><b>US0</b> <i><a href="#AT91C_US0_US">AT91C_US0_US</a></i> 0xFFFC0100</font></null></ul></null><hr></html>
